The invention relates to a transmission system comprising at least a transmission device for exchanging transport modules in signals of a synchronous multiplex hierarchy, which signals have a frame structure of columns and rows, by means of a switching network.
The invention likewise relates to a transmission device for this transmission system.
A synchronous multiplex hierarchy makes it possible to combine, divide, reroute, or enter arbitrary signal groups in a memory in a transmission system. Examples of a synchronous multiplex hierarchy are SONET and the Synchronous Digital Hierarchy. For example, the plesiochronous datachannel signal streams (in Europe: 2 Mbit/s, 34 Mbit/s and 140 Mbit/s) arriving at a transmission device can be edited with a mapping instruction, so that they are always transmitted in a uniform synchronous transport module frame (STM-1 frame) 125 .mu.s in length as an STM-1 signal at a bit rate of 155.52 Mbit/s over the transmit path. Such a network junction may also receive and further process the higher bit rate STM-N signals (N =4,16, . . . ) resulting from multiplexed STM-1 signals.
The STM-1 signal is structured in frames and comprises, in addition to the actual payload of the signal, control indication bits and justification data. An STM-1 frame comprises 270 columns and 9 rows ( 270 bytes per row). The rows 1 to 3 and 5 to 9, in all the columns 1 to 9 carry the section over head (SOH) for control indication bytes and error detection information bytes and the rest of the structure (AU-payload) carries data of the signal, justification data and further overhead bytes.
A plurality of different containers (C-4, C-3, C-2, C-12 and C-11) can be accommodated in the AU-payload. A container is understood to mean the basic unit for carriage of digital payload. For example, an STM-1 frame can comprise an administrative unit AU-4 with a container C-4 for data blocks of a signal having a bit rate of 139.264 Mbit/s. Alternatively, it is possible that three administrative units AU-3 are accommodated in the STM-1 frame. For example, one administrative unit AU-3 thereof comprises a container C-3 for data blocks of a signal having a bit rate of 44.736 Mbit/s. The second administrative unit AU-3 can comprise, for example, seven tributary unit groups TUG-2 having each one container C-2 for data blocks of a signal having a 6.312 Mbit/s bit rate. Seven TUG-2s having each three containers C-12 for data blocks of a signal having a bit rate of 2.048 Mbit/s can further be mapped into the third administrative unit AU-3.
By appending control indication bits, containers become virtual containers (for example, VC-4, VC-3, VC-2, VC-12, VC-11 in an STM-1 signal), and by appending pointer bytes and justification indication bytes specific virtual containers (for example, VC-3, VC-2, VC-12, VC-11 in an STM-1 signal) become tributary units (for example, TU-3, TU-2, TU-12, TU-11, in an STM-1 signal). Specific virtual containers and tributary units will be referenced transport modules in the following. A transport module is understood to mean virtual containers that have not been mapped into further virtual containers (e.g. VC-4 into AU-4 and VC-3 into AU-3 in an STM-1 signal) and also tributary units (e.g. TU-3, TU-2, TU-12, TU-11 in an STM-1 signal).
The transport modules can be classified in higher-order and lower-order transport modules. A higher-order transport module is understood to mean a transport module that comprises lower-order transport modules and does not form part of a further transport module. A lower-order transport module is contained in a higher-order transport module. With an STM-1 signal, for example the virtual container VC-4 contained in an AU-4 or a virtual container VC-3 contained in an AU-3 is denoted a higher-order transport module. Lower-order transport modules in an STM-1 signal are the TU-3, TU-2, TU-12 and TU-11.
EP-A2-0 407 851 has disclosed said transmission system. The system comprises a plurality of transmission devices (cross connectors) which extract or map various transport modules of an STM-1 signal by means of a switching network, or assembles STM-1 signals. For this purpose is used an additional frame structure (frame structured auxiliary signal) different from the STM-1 frame.
It is an object of the invention to provide a transmission system which makes an exchange possible of transport modules in signals of the synchronous hierarchy in another manner.
This object is achieved in a transmission system of the type defined in the opening paragraph, in that at least an adapter circuit is provided to delay at least a higher-order transport module up to a given position in the adapted frame structured signal and in that the switching network comprises at least a time stage provided to write and identify column by column the bytes to be stored of an adapted frame structured signal and to read out the bytes identified column by column in a given order to form at least an outgoing frame structured signal.
The transmission system according to the invention transmits frame structured signals of the Synchronous Digital Hierarchy. In at least one transmission device of the transmission system lower-order transport modules of at least a frame structured signal are exchanged or also mapped into another frame structured signal. For this purpose, an adaptation of the frame format is first carried out in an adapter circuit associated to a frame structured signal. A higher-order transport module is then delayed for such a period of time that the higher-order transport module takes up a predetermined position in the frame. For example, a virtual container VC-4 (higher-order transport module) can be delayed for such a long time that the first byte of the VC-4 lies in the first row and the tenth column of the STM-1 frame. With such an. adaptation of the frame format the bytes of a lower-order transport module can be detected in a simple manner. For as a result of this adaptation only bytes of a lower-order transport module occur in certain columns of the STM-1 frame. The new frame structured signal to be formed can then be compiled in a simple manner in the switching network by taking certain columns of at least an adapted signal. In the switching network the bytes of an adapted frame structured signal are therefore written each time in a time stage and identified column by column. The bytes are then read out in a given order.
The bytes for the section over head (SOH) may also be given by the switching network or alternatively be compiled in another circuit.
In addition to an adaptation of the frame format, also a synchronization is carried out in the adapter circuit, because there are usually frequency fluctuations between the clock signal (write clock signal) derived from the incoming frame structured signal and the local clock signal (read clock signal). The adapter circuit is provided to comprise a buffer arrangement for synchronizing the frame structured signal to be written which is coupled to a write clock signal, and for synchronizing the frame structured signal to be read out which is coupled to a read clock signal, and to include a control circuit for inserting justification bytes into the lower-order transport modules of the frame structured signal to be read out in the event of a difference between write clock signal frequency and read clock signal frequency. A synchronization is thus realised by inserting justification bytes into the frame structured signal to be read out from the buffer. There is a positive justification action if the read clock signal is larger than the write clock signal. With a reversed ratio there is a negative justification action. With a positive justification action data gaps are inserted. With a negative justification action a payload byte is transported in lieu of a data gap.
To delay a higher-order transport module in the adapter circuit at least up to a given position, justification bytes (data gaps) are inserted when the adapted frame structured signal is compiled. When a higher-order transport module is synchronized and delayed, a virtual container in a lower-order transport module may be shifted in such a way that the delay of the lower-order transport module between the frame structured signal fed to the adapter circuit and the adapted frame structured signal is smaller than the delay of the higher-order transport module.
It is not only possible to exchange transport modules of various frame structured signals, but also bytes of lower-order transport modules can be extracted or mapped into an STM-1 signal. The space stage of the switching network is then provided to transport
the bytes of frame-synchronized signals produced by the time stages at specific outputs of the space stage to compile outgoing frame structured signals, PA1 the bytes of a transport module produced by a time stage at a specific output of the space stage to compile a signal with bytes of a lower-order transport module, and PA1 a signal to be received comprising a transport module at an output of the space stage to map the bytes of the transport module into an outgoing frame structured signal.
With this embodiment lower-order transport modules are exchanged between at least two frame structured signals. The space stage contained in the switching network provides that the incoming bytes of a time stage are presented at specific outputs of the space stage. Such an output presents either a newly compiled frame structured signal or a signal comprising bytes of a transport module, which signal has the same bit rate as the frame structured signal. Besides the bytes of the transport module there are also data gaps in the signal. In a subsequent circuit the data gaps can be largely removed. For example, the transport module contained in an STM-1 signal having a bit rate of about 155 Mbit/s can be accommodated in a signal having a bit rate of about 2 Mbit/s by means of a buffer.
Furthermore, bytes of a transport module may also be mapped into a frame structured signal. For this purpose, the associated bytes of the transport module are presented at the output of the space stage which supplies the frame structured signal.
If the frame structured signal is an STM-1 signal, an adapter circuit is used either to delay a virtual container VC-4 or a virtual container VC-3 in an administrative unit AU-3 up to a given position in the STM-1 frame. The higher-order transport modules in the STM-1 signal are thus the virtual container VC-4 and the virtual container VC-3, if they are mapped into an administrative unit AU-3. A virtual container VC-3 which is mapped into a TU-3 is not associated to the higher-order transport modules. The TU-3 is to be considered a lower-order transport module.
In an embodiment of the switching network it is provided that a time stage of the switching network comprises a detection circuit for recognizing the beginning of a frame of an STM-1 signal, a memory circuit to buffer bytes of an STM-1 signal, a write address generator controlled by the detection circuit and a read address generator controlled by the detection circuit and in that the switching network comprises a setting circuit for producing the order in which the bytes are to be read out from the memory circuit and the connecting lines for the space stage.
The write address generator controlled by the detection circuit comprises a first counter arrangement with a column counter for supplying addresses for the write operation of the memory circuit. Once the detection circuit has detected the beginning of an STM-1 frame, it sets the column counter arranged, for example, as a modulo counter of the first counter arrangement to an initial value. The value of 270 may be selected as the modulo factor, which value corresponds exactly to the number of columns of an STM-1 frame.
The read address generator likewise controlled by the detection circuit comprises a second counter arrangement with a column counter and a first Table memory. The second counter arrangement is provided to supply addresses for the first Table memory. The first Table memory is used for translating an address supplied by the second counter arrangement into a specific stored address for the read process of the memory circuit. The setting circuit is provided to feed the translation Table to the first Table memory.
The detection circuit sets the column counter arranged as a modulo counter of the second counter arrangement to an initial value once the circuit has detected the beginning of an STM-1 frame. The value of 270 can be selected as a modulo factor, which exactly corresponds to the number of columns of an STM-1 frame.
A setting value generator is used for controlling the space stage of the switching network. This generator controlled by the detection circuit of a time stage comprises a third counter arrangement with a column counter and a second Table memory. The counter arrangement is provided to, supply addresses for the second Table memory. The second Table memory is intended for the translation of an address supplied by the counter arrangement into specific setting values for the connecting lines of the space stage. The setting circuit is additionally used for feeding the translation Table to the second Table memory. In the space stage of the switching network the connecting lines are switched column by column. Setting values supplied by a second Table memory are used to set the connecting lines. The second Table memory translates the addresses supplied by the third counter arrangement on the basis of its stored translation Table.
Furthermore, the first counter arrangement and the first Table memory are only provided to supply least significant bits of the counter or memory value. On the basis of repetitive columns of a lower-order transport module (e.g. 3 columns are each time assigned to 84 TU-11, 4 columns are each time assigned to 63 TU-12), the memory circuit may comprise a time stage of 180 memory locations (2*90 columns) in lieu of 540 memory locations (2*270 columns).
The section overhead (SOH) may be given by the transmission device or newly assembled in a parallel arranged device. If the SOH is newly assembled in a parallel arranged device, the SOH bytes are not stored in the memory circuit of a time stage. Therefore, the first, second and third counter arrangements further include a row counter, an evaluation circuit and a release circuit. The row counter controlled by the column counter and the column counter are provided to supply their counts to the evaluation circuit. The evaluation circuit is used for supplying a release value to the release circuit at least if there is no SOH present. The release circuit is intended to release an address supplied by the column counter if a release value is available.